This page is not encouraging regarding control of access to physical memory. Worry about this. To be thwarted
Matt Rice refers me to this which is encouraging. That picture should also note that the IOMMU is hardware that is controlled somehow by the privileged code of the CPU. The link is also useful for terminology which is useful to find specs by hardware builders who confirm such information.
The link above leads to this page by NVIDIA which introduces some information that I had not seen. It describes mechanisms that suggest to me that engineers still worry about the integrity of main memory in the presence of hostile CPU and GPU code.
Wikipedia’s article on the IOMMU has a good history of these ideas with pointers to various specifications.
On the candidate systems, how do pixels get from GPU to screen?
Two possibly related problems persist: