Here is my dim conception of a DDR4 chip in 2012. Alas some of the stuff below is from memory of DDR3 details. I have described a chimera.

This is a middle of the design space chip. There are 22 memory banks on the chip. (Doc refers to ‘bank group’ where I use ‘bank’.) Each memory bank has 215 rows. Each row has 210 wrds. Each wrd has 24 bits. In all 231 bits per chip. There is a regen register (regeneration) for each bank. Each regen register has 210 wrds. In the neutral chip state all banks are closed. One command to the chip opens a specified bank and a row within; the content of that row is moved from the bank to the regen register and lost in the bank. Chip commands to read or write data specify which regen register and which wrd of that register. Two wrd transfers to or from subsequent parts of the same row. A close command to the chip specifies the bank and that regen register information is put back in the bank proper, possibly modified. One wrd of data can cross the data pins on both the rising and falling GHz clock. The chip can respond to new wrd addresses each clock unless other less frequent commands must be performed.

As time permits rows in the banks are refreshed.

Better but more dilute information in Wikipedia (2014 Dec)