Digital Quadrature Heterodyne

This idea may be infeasible or very expensive to implement. The notion serves to define what I think a Quadrature Heterodyne does. It might serve to test ideas and designs thru simulation. The logic I speculate on here needs to be hardware, either analog or digital; software is too slow except for exploratory purposes.

Using the parameter names given here we assume that 1 ≤ k = fd2^–n ≤ 16. k is the number of intermediate frequency cycles that occur during one sample period. We choose f to make k an integer. Assume that we executed the following code regularly with frequency 4f:

a += antenna; {samp t = -a; a = b; b = c; c = d; d = t;}

After every 4k of these events we send the complex number (a–c, b–d) to memory and reset a, b, c and d. These are the values said elsewhere to constitute the heterodyne yield. a, b, c and d are fixed point numbers each big enough to hold k times the largest fixed point antenna reading.

We thus sample at twice the Nyquist rate.

I saw the following idea for a fast A to D converter about 1960. Imagine a systolic array of about 4 to 6 of the following devices. The array need not be clocked. Each device inputs one analog signal S_i whose level is between 0 and 1. Each device outputs a like output signal S_o, and a bit as well.

S_o = if S_i<1/2 then 1-2S_i else 2S_i-1
b_o = S_i<1/2

Note that S_o is a continuous function of S_i and can presumably be produced by a diode and amplifier. The output bits are unclocked but if we pick up these bits from the systolic array at times characteristic of the innate time delay thru the array, then we gather a Gray coded binary value for the signal. As a value changes by a small amount, at most one bit of its gray code changes. I suspect that this systolic array must actually be clocked. I am well beyond my depth here. There is add logic for adding Gray coded binary numbers. Certainly if the adds are done in ordinary binary they must be clocked.

A little thought shows that this logic is trivially parallelized except for the discretization of the signal from the antenna. This is the same sort of problem solved by circuits which grab 10GHz bit streams from optical fibers. If turbo codes are used there then even the AD logic would come from fiber practice.