I think that there is a simple hardware-software solution to the synchrony problem where a signal seems to arrive before it was sent, due to mis-set clocks.

Within a tight SMP configuration there is generally a clock that counts each clock tick. If the sender reads this clock and sends a message to another program in the same clock regime, and the recipient reads the same clock, the recipient will see a greater time.

Special precautions are necessary whenever signals cross clock domains. We add another element to those precautions. Ascribe an ATI value to the signal derived from the source cycle clock. In the recipient’s clock domain hold the signal in quarantine until the recipient’s clock reaches the value whose ATI value matches or exceeds the value in the message. Such a signal will never arrive before it was sent.

This protocol is not needed at clock domain boundaries where the message is not consulted, as in the clocks of switching nodes. Those nodes must preserve the TAI value however. The nodes may be miles or continents apart.

Some machines will still have mis-set theories of ATI and conversations with such machines will have an additional latency with that additional delay. If the error is large the quarantine buffer will overflow and the error will be manifest. A machine with low confidence in its ATI value will believe TAI values that arrive from more credibility. This is a classic trust network.


‘Ascribing’ is slightly messy. Perhaps it is easier to present TAI to the application program.