Some memory technologies, especially core, were destructive read. Externally there were separate memory read and write operations while internally there were separate read and write cycles, but there was not the obvious connection between external operations and internal cycles. A read cycle would destroy the information in the medium as it was read. A write cycle was thus required to restore the information in memory. This is called the regeneration cycle and meantime the information resides in the memory register or regen register. On most systems the read cycle would leave zeros in memory. On such systems the write operation is actually an OR to memory, due to the nature of the medium and control circuitry.

Here are occasions where one of these cycles may be omitted:

  1. If the desired operation is “OR to memory” then it suffices to omit the read cycle.
  2. If the operation is to add to memory then the addition can be done between the read cycle and write cycle.
  3. If the operation is to shift memory by a small number of words then that many words must first be cleared at the destination, and then half-reads and half-writes suffice for the rest. This leaves 0’s in the vacated locations which may be OK.
  4. An operation to store 0 is merely a bare read cycle.
Modern DRAMs do much the same. Reading a row of the DRAM bank is highly analogous to the read cycle for core. The bits are ruined in their home location for their charge is used to drive a signal down the bit lines to the sense amps and thence to a register to keep the only copy of the data until the end of the cycle. The other half of the cycle is called ‘precharge’ for rumored reasons which I can’t explain. ‘Recharge’ would describe this action well as it puts back the charge in the capacitor which is the home location of the memory bits.

The same tricks would work for DRAM but the modern cache generally gets in the way. Perhaps split cycle tricks work in the cache proper, for some cache designs. ECC ruins tricks 1 & 2.